View AD80066KRSZ_4622880.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Complete 16-Bit CCD/CIS Signal Processor AD80066
FEATURES
16-bit, 24 MSPS analog-to-digital converter (ADC) 4-channel operation up to 24 MHz (6 MHz/channel) 3-channel operation up to 24 MHz (8 MHz/channel) Selectable input range: 3 V or 1.5 V peak-to-peak Input clamp circuitry Correlated double sampling 1x~6x programmable gain 300 mV programmable offset Internal voltage reference Multiplexed byte-wide output Optional single-byte output mode 3-wire serial digital interface 3 V/5 V digital I/O compatibility Power dissipation: 490 mW at 24 MHz operation Reduced power mode and sleep mode available 28-lead SSOP package
GENERAL DESCRIPTION
The AD80066 is a complete analog signal processor for imaging applications. It features a 4-channel architecture designed to sample and condition the outputs of linear charged coupled device (CCD) or contact image sensor (CIS) arrays. Each channel consists of an input clamp, correlated double sampler (CDS), offset digitalto-analog converter (DAC), and programmable gain amplifier (PGA), multiplexed to a high performance 16-bit ADC. For maximum flexibility, the AD80066 can be configured as a 4-channel, 3-channel, 2-channel, or 1-channel device. The CDS amplifiers can be disabled for use with sensors that do not require CDS, such as CIS and CMOS sensors. The 16-bit digital output is multiplexed into an 8-bit output word, which is accessed using two read cycles. There is an optional single-byte output mode. The internal registers are programmed through a 3-wire serial interface and enable adjustment of the gain, offset, and operating mode. The AD80066 operates from a 5 V power supply, typically consumes 490 mW of power, and is packaged in a 28-lead SSOP.
APPLICATIONS
Flatbed document scanners Film scanners Digital color copiers Multifunction peripherals
AVDD AVSS CML AVDD AVSS
FUNCTIONAL BLOCK DIAGRAM
CAPT CAPB DRVDD DRVSS
VINA
CDS 9-BIT DAC
PGA
BAND GAP REFERENCE
AD80066
VINB
CDS 9-BIT DAC
PGA
4:1 MUX
16-BIT ADC
16
16:8 MUX
8
DOUT (D[0:7])
VINC
CDS 9-BIT DAC
PGA
CONFIGURATION REGISTER DIGITAL CONTROL INTERFACE
SCLK SLOAD SDATA
MUX REGISTER PGA 6 CH. A CH. B CH. C CH. D
VIND
CDS 9-BIT DAC
GAIN REGISTERS
OFFSET
INPUT CLAMP BIAS
9
CH. A CH. B CH. C CH. D
OFFSET REGISTERS ADCCLK
08552-001
CDSCLK1
CDSCLK2
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
AD80066 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Analog Specifications ................................................................... 3 Digital Specifications ................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 4-Channel CDS Mode................................................................ 13 4-Channel SHA Mode................................................................ 13 1-Channel CDS Mode ............................................................... 13 1-Channel SHA Mode ............................................................... 13 Internal Register Map .................................................................... 14 Internal Register Details ................................................................ 15 Configuration Register .............................................................. 15 Mux Register ............................................................................... 15 PGA Gain Registers ................................................................... 15 Offset Registers ........................................................................... 15 Circuit Operation ........................................................................... 17 Analog Inputs--CDS Mode ...................................................... 17 External Input Coupling Capacitors ........................................ 17 Analog Inputs--SHA Mode ...................................................... 18 Programmable Gain Amplifiers (PGA) .................................. 18 Applications Information .............................................................. 19 Circuit and Layout Recommendations ................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
4/10--Revision A: Initial Version
Rev. A | Page 2 of 20
AD80066 SPECIFICATIONS
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, PGA gain = 1, unless otherwise noted. Table 1.
Parameter MAXIMUM CONVERSION RATE 4-Channel Mode with CDS 3-Channel Mode with CDS 2-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY (ENTIRE SIGNAL PATH) ADC Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes ANALOG INPUTS Input Signal Range 1 Allowable Reset Transient1 Input Limits 2 Input Capacitance Input Bias Current AMPLIFIERS PGA Gain Range PGA Gain Resolution2 PGA Gain Monotonicity Programmable Offset Range Programmable Offset Resolution Programmable Offset Monotonicity NOISE AND CROSSTALK Total Output Noise at PGA Minimum Total Output Noise at PGA Maximum Channel-to-Channel Crosstalk @ 24 MSPS @ 12 MSPS POWER SUPPLY REJECTION AVDD = 5 V 0.25 V VOLTAGE REFERENCE (TA = 25C) CAPT - CAPB TEMPERATURE RANGE Operating Storage POWER SUPPLIES AVDD DRVDD OPERATING CURRENT AVDD DRVDD Power-Down Mode Current Min Typ 24 24 24 12 16 +20/-5 0.5 Guaranteed 1.5/3.0 2.0 AVSS - 0.3 10 10 1 64 Guaranteed -305 512 Guaranteed 9.5 35 70 90 0.1 0.75 0 -65 4.5 3.0 5.0 3.3 95 4 300 70 +150 5.25 5.25 +295 5.9 AVDD + 0.3 Max Unit MSPS MSPS MSPS MSPS Bits LSB LSB
V p-p V V pF nA V/V Steps mV Steps
LSB rms LSB rms dB dB % FSR V C C V V mA mA A
Rev. A | Page 3 of 20
AD80066
Parameter POWER DISSIPATION 4-Channel Mode at 24 MHz 1-Channel Mode at 12 MHz 4-Channel Mode at 8 MHz, Slow Power Mode 3
1 2 3
Min
Typ 490 300 165
Max
Unit mW mW mW
The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see Figure 2). The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the Programmable Gain Amplifiers (PGA) section for more information). Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation.
AVDD = 5V
08552-002
2V TYP RESET TRANSIENT
3V BIAS SET BY INPUT CLAMP 1.5V OR 3V p-p MAX INPUT SIGNAL RANGE GND
Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, CL = 10 pF, unless otherwise noted. Table 2.
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS (DRVDD = 5 V) High Level Output Voltage (IOH = 2 mA) Low Level Output Voltage (IOL = 2 mA) LOGIC OUTPUTS (DRVDD = 3 V) High Level Output Voltage (IOH = 2 mA) Low Level Output Voltage (IOL = 2 mA) Symbol VIH VIL IIH IIL CIN VOH VOL VOH VOL Min 2.0 0.8 10 10 10 4.5 0.5 2.5 0.5 Typ Max Unit V V A A pF V V V V
Rev. A | Page 4 of 20
AD80066
TIMING SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V. Table 3.
Parameter CLOCK PARAMETERS 4-Channel Pixel Rate 1-Channel Pixel Rate ADCCLK Pulse Width CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK1 Falling 1 to CDSCLK2 Rising ADCCLK Falling to CDSCLK2 Rising CDSCLK2 Rising to ADCCLK Rising CDSCLK2 Falling1 to ADCCLK Falling CDSCLK2 Falling1 to CDSCLK1 Rising Aperture Delay for CDS Clocks SERIAL INTERFACE Maximum SCLK Frequency, Write Operation Maximum SCLK Frequency, Read Operation SLOAD to SCLK Setup Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Setup Time SCLK Rising to SDATA Hold Time SCLK Falling to SDATA Valid DATA OUTPUT Output Delay Latency (Pipeline Delay)
1
Symbol tPRA tPRB tADCCLK tC1 tC2 tC1C2 tADC2 tC2ADR tC2ADF tC2C1 tAD fSCLK fSCLK tLS tLH tDS tDH tRDV tOD
Min 166 83 20 15 15 0 0 5 20 5
Typ
Max
Unit ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns
2 50 25 5 5 2 2 10 8 3 (fixed)
ns Cycles
CDSCLKx falling edges should not occur within the first 10 ns following an ADCCLK edge.
Timing Diagrams
tPRA
ANALOG INPUTS
tAD tC1
PIXEL n (A,B,C,D)
PIXEL (n + 1)
tAD tC2C1 tC1C2 tC2 tC2ADF
CDSCLK1
CDSCLK2
tADCCLK
ADCCLK
tADC2
tC2ADR
tADCCLK
OUTPUT DATA (D[7:0])
tOD
A(n) HIGH BYTE A(n) LOW BYTE B(n) HIGH BYTE
08552-003
B(n - 2) C(n - 2) C(n - 2) D(n - 2) D(n - 2) A(n - 1) A(n - 1) B(n - 1) B(n - 1) C(n - 1) C(n - 1) D(n - 1) D(n - 1) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE
Figure 3. 4-Channel CDS Mode Timing
Rev. A | Page 5 of 20
AD80066
PIXEL n (A, B, C) ANALOG INPUTS PIXEL (n + 1) PIXEL (n + 2)
tAD tAD tC1 tC2C1 tPRA
CDSCLK1
tC1C2
CDSCLK2
tC2 tC2ADF
tADCCLK
ADCCLK
tADC2
tC2ADR
tADCCLK
OUTPUT DATA (D[7:0])
tOD
A(n) HIGH BYTE A(n) LOW BYTE B(n) HIGH BYTE B(n) LOW BYTE
08552-004 08552-005
A(n - 2) B(n - 2) B(n - 2) C(n - 2) C(n - 2) A(n - 1) A(n - 1) B(n - 1) B(n - 1) C(n - 1) C(n - 1) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE
Figure 4. 3-Channel CDS Mode Timing
PIXEL n ANALOG INPUTS
tAD tAD tC1 tC2C1
PIXEL (n + 1)
PIXEL (n + 2)
tPRA
CDSCLK1
tC1C2
tC2
CDSCLK2
tC2ADR tADC2 tC2ADF
ADCCLK
tADCCLK
OUTPUT DATA (D[7:0]) CH 1 (n - 2) HIGH BYTE LOW BYTE
tADCCLK
CH 2 (n - 2) HIGH BYTE LOW BYTE CH 1 (n - 1) HIGH BYTE LOW BYTE CH 2 (n - 1) HIGH BYTE LOW BYTE CH 1 (n) HIGH BYTE LOW BYTE
Figure 5. 2-Channel CDS Mode Timing
Rev. A | Page 6 of 20
AD80066
PIXEL n ANALOG INPUTS PIXEL (n + 1) PIXEL (n + 2)
tAD tAD
tC1
tC2C1
tPRB
CDSCLK1
tC1C2
tC2
CDSCLK2 tC2ADR
tC2ADF
ADCCLK
tADCCLK tADCCLK
tOD PIXEL (n - 3) HIGH BYTE PIXEL (n - 3) LOW BYTE PIXEL (n - 2) HIGH BYTE PIXEL (n - 2) LOW BYTE
OUTPUT DATA (D[7:0])
PIXEL (n - 4) HIGH BYTE
PIXEL (n - 4) LOW BYTE
NOTES 1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS LOW.
Figure 6. 1-Channel CDS Mode Timing
PIXEL n (A, B, C, D)
ANALOG INPUTS
PIXEL (n + 1)
tAD
tPRA tC2
CDSCLK2
tC2ADF tADCCLK
tADC2
tC2ADR
ADCCLK
tADCCLK
OUTPUT DATA (D[7:0])
tOD
D(n) HIGH BYTE D(n) LOW BYTE A(n) HIGH BYTE A(n)
08552-007
B(n - 2) C(n - 2) C(n - 2) D(n - 2) D(n - 2) A(n - 1) A(n - 1) B(n - 1) B(n - 1) C(n - 1) C(n - 1)
HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE
LOW BYTE
Figure 7. 4-Channel SHA Mode Timing
Rev. A | Page 7 of 20
08552-006
AD80066
PIXEL n ANALOG INPUTS
PIXEL (n + 1)
tAD
tPRB tC2
CDSCLK2
tC2ADR
ADCCLK
tC2ADF tADCCLK
tADCCLK
OUTPUT DATA (D[7:0])
PIXEL (n - 4) HIGH BYTE PIXEL (n - 4) LOW BYTE
tOD
PIXEL (n - 3) HIGH BYTE PIXEL (n - 3) LOW BYTE PIXEL (n - 2) HIGH BYTE PIXEL (n - 2)
08552-008
08552-009
LOW BYTE
Figure 8. 1-Channel SHA Mode Timing
ADCCLK
tOD
OUTPUT DATA (D[7:0]) HIGH BYTE (DB[15:8]) PIXEL n LOW BYTE (DB[7:0]) PIXEL n
tOD
HIGH BYTE (DB[15:8]) PIXEL (n + 1) LOW BYTE (DB[7:0]) PIXEL (n + 1) LOW BYTE (DB[7:0]) PIXEL (n + 2) HIGH BYTE (DB[15:8]) PIXEL (n + 3)
Figure 9. Digital Output Data Timing
ADCCLK
tOD
OUTPUT DATA (D[7:0]) HIGH BYTE (DB[15:8]) PIXEL n HIGH BYTE (DB[15:8]) PIXEL (n + 1) HIGH BYTE (DB[15:8]) PIXEL (n + 2)
Figure 10. Single-Byte Mode Digital Output Data Timing
SDATA R/W A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
tDH
SCLK
tDS
tLS
SLOAD
tLH
08552-011
Figure 11. Serial Write Operation Timing
SDATA R/W A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
tRDV
SCLK tL S SLOAD
tLH
08552-012
Figure 12. Serial Read Operation Timing
Rev. A | Page 8 of 20
08552-010
AD80066 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter VINx, CAPT, CAPB Digital Inputs SDATA AVDD DRVDD AVSS Digital Outputs (D[7:0]) Temperature Junction Storage Lead (10 sec) With Respect To AVSS AVSS DRVSS AVSS DRVSS DRVSS DRVSS Rating -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to DRVDD -0.5 V to +6.5 V -0.5 V to +6.5 V -0.3 V to +0.3 V -0.3 V to DRVDD + 0.3 V
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance
Package Type 28-Lead, 5.3 mm SSOP JA 109 JC 39 Unit C/W
ESD CAUTION
150C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. A | Page 9 of 20
AD80066 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD 1 CDSCLK1 CDSCLK2 ADCCLK DRVDD
2 3 4 5 28 27 26 25 24 23
AVSS VINA OFFSET VINB CML VINC CAPT CAPB VIND AVSS AVDD SLOAD SDATA
08552-013
DRVSS 6 (MSB) D7 7 D6 8 D5 9 D4 10 D3 11 D2 12 D1 13 (LSB) D0 14
TOP VIEW (Not to Scale)
AD80066
22 21 20 19 18 17 16 15
SCLK
Figure 13. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1
Mnemonic AVDD CDSCLK1 CDSCLK2 ADCCLK DRVDD DRVSS D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) SDATA SCLK SLOAD AVDD AVSS VIND CAPB CAPT VINC CML VINB OFFSET VINA AVSS
Type 1 P DI DI DI P P DO DO DO DO DO DO DO DO DI/DO DI DI P P AI AO AO AI AO AI AO AI P
Description 5 V Analog Supply. CDS Reference Level Sampling Clock. CDS Data Level Sampling Clock. ADC Sampling Clock. Digital Output Driver Supply (3 V or 5 V). Digital Output Driver Ground. Data Output MSB. ADC DB15 high byte; ADC DB7 low byte. Data Output. ADC DB14 high byte; ADC DB6 low byte. Data Output. ADC DB13 high byte; ADC DB5 low byte. Data Output. ADC DB12 high byte; ADC DB4 low byte. Data Output. ADC DB11 high byte; ADC DB3 low byte. Data Output. ADC DB10 high byte; ADC DB2 low byte. Data Output. ADC DB9 high byte; ADC DB1 low byte. Data Output LSB. ADC DB8 high byte; ADC DB0 low byte. Serial Interface Data Input/Output. Serial Interface Clock Input. Serial Interface Load Pulse. 5 V Analog Supply. Analog Ground. Analog Input, D Channel. ADC Bottom Reference Voltage Decoupling. ADC Top Reference Voltage Decoupling. Analog Input, C Channel. Internal Bias Level Decoupling. Analog Input, B Channel. Clamp Bias Level Decoupling. Analog Input, A Channel. Analog Ground.
AI = analog input, AO = analog output, DI = digital input, DO = digital output, and P = power.
Rev. A | Page 10 of 20
AD80066 TYPICAL PERFORMANCE CHARACTERISTICS
1.0
15
0.5
10
DNL (LSB)
0
INL (LSB)
08552-014
5
-0.5
0
0
12,800
25,600
38,400
51,200
64,000
0
12,800
25,600
38,400
51,200
64,000
ADC OUTPUT CODE
ADC OUTPUT CODE
Figure 14. Typical DNL Performance
Figure 16. Typical INL Performance
50 45 40
OUTPUT NOISE (LSB)
35 30 25 20 15 10 5 0 15 30 45 63
08552-015
0
PGA REGISTER VALUE (Decimal)
Figure 15. Output Noise vs. PGA Gain
Rev. A | Page 11 of 20
08552-016
-1.0
-5
AD80066 TERMINOLOGY
Integral Nonlinearity (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value; therefore, every code must have a finite width. No missing codes guaranteed to 16-bit resolution indicates that all 65,536 codes must be present over all operating ranges. Offset Error The first ADC code transition should occur at a level 1/2 LSB above the nominal zero-scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog value 11/2 LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. Input-Referred Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and converted to an equivalent voltage, using the relationship 1 LSB = 1.5 V/65,536 = 23 V. The noise is then referred to the input of the AD80066 by dividing by the PGA gain. Channel-to-Channel Crosstalk In an ideal 3-channel system, the signal in one channel does not influence the signal level of another channel. The channel-tochannel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. In the AD80066, one channel is grounded and the other two channels are exercised with full-scale input signals. The change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB. Aperture Delay The aperture delay is the delay that occurs from when a sampling edge is applied to the AD80066 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low; therefore, the aperture delay is measured from each falling edge of the clock to when the internal sample is taken. Power Supply Rejection The power supply rejection specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits.
Rev. A | Page 12 of 20
AD80066 THEORY OF OPERATION
The AD80066 can be operated in several different modes, including 4-channel CDS mode, 4-channel SHA mode, 1-channel CDS mode, and 1-channel SHA mode. Each mode is selected by programming the configuration register through the serial interface. For more information on CDS or SHA mode operation, see the Circuit Operation section. SHAs are modified by the offset DACs and then scaled by the four PGAs. The outputs of the PGAs are then multiplexed through the 16-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The input signal is sampled with respect to the voltage applied to the OFFSET pin (see Figure 19). With the OFFSET pin grounded, a 0 V input corresponds to the zero-scale output of the ADC. The OFFSET pin can also be used as a coarse offset adjustment pin. A voltage applied to this pin is subtracted from the voltages applied to the A, B, C, and D inputs in the first amplifier stage of the AD80066. The input clamp is disabled in this mode. For more information, see the Analog Inputs--SHA Mode section. The offset and gain values for the A, B, C, and D channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the mux register. Timing for this mode is shown in Figure 7. The CDSCLK1 pin should be grounded in this mode. Although not required, the falling edge of CDSCLK2 should occur coincident with or before the rising edge of ADCCLK. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is 3 ADCCLK cycles.
4-CHANNEL CDS MODE
In 4-channel CDS mode, the AD80066 simultaneously samples the A, B, C, and D input voltages from the CCD outputs. The sampling points for each CDS are controlled by CDSCLK1 and CDSCLK2 (see Figure 17 and Figure 18). The CDSCLK1 falling edge samples the reference level of the CCD waveform, and the CDSCLK2 falling edge samples the data level of the CCD waveform. Each CDS amplifier outputs the difference between the CCD reference level and the data level. The output voltage of each CDS amplifier is then level-shifted by an offset DAC. The voltages are scaled by the four PGAs before being multiplexed through the 16-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The offset and gain values for the A, B, C, and D channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the mux register. Timing for this mode is shown in Figure 3. The falling edge of CDSCLK2 should occur coincident with or before the rising edge of ADCCLK. However, this is not required to satisfy the minimum timing constraints. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is 3 ADCCLK cycles.
1-CHANNEL CDS MODE
The 1-channel CDS mode operates in the same way as the 4-channel CDS mode, except the multiplexer remains fixed. Only the channel specified in the mux register is processed. Timing for this mode is shown in Figure 6.
1-CHANNEL SHA MODE
The 1-channel SHA mode operates in the same way as the 4-channel SHA mode, except the multiplexer remains fixed. Only the channel specified in the mux register is processed. Timing for this mode is shown in Figure 8. The CDSCLK1 pin should be grounded in this mode of operation.
4-CHANNEL SHA MODE
In 4-channel SHA mode, the AD80066 simultaneously samples the A, B, C, and D input voltages. The sampling point is controlled by CDSCLK2. The falling edge of CDSCLK2 samples the input waveforms on each channel. The output voltages from the three
Rev. A | Page 13 of 20
AD80066 INTERNAL REGISTER MAP
Table 7. Internal Register Map
Register Name Configuration Mux Gain A Gain B Gain C Gain D Offset A Offset B Offset C Offset D A3 0 0 0 0 0 0 0 0 1 1 Address A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 A0 0 1 0 1 0 1 0 1 0 1 D8 0 0 0 0 0 0 MSB MSB MSB MSB D7 0 0 0 0 0 0 D6 0 0 0 0 0 0 D5 VREF 0 MSB MSB MSB MSB D4 2/1 byte Ch. order Data Bits D3 CDS on Ch. A D2 Input range Ch. B D1 Fast/slow Ch. C D0 Power on Ch. D LSB LSB LSB LSB LSB LSB LSB LSB
Rev. A | Page 14 of 20
AD80066 INTERNAL REGISTER DETAILS
CONFIGURATION REGISTER
The configuration register controls the AD80066 operating mode and bias levels. The D8, D7, and D6 bits should always be set low. Bit D2 sets the full-scale input voltage range of the AD80066 ADC to either 3 V (high) or 1.5 V (low). Bit D5 controls the internal voltage reference. If the AD80066 internal voltage reference is used, this bit is set low. Setting Bit D5 high disables the internal voltage reference, allowing an external voltage reference to be used. Setting Bit D3 low enables the CDS mode of operation and setting this bit high enables the SHA mode of operation. If Bit D4 is set high, the 16-bit ADC output is multiplexed into two bytes. The most significant byte is output on the ADCCLK rising edge, and the least significant byte is output on the ADCCLK falling edge (see Figure 10). If Bit D1 is set high, the AD80066 is configured for slow operation (8 MHz) to reduce power consumption. Bit D0 controls the power-down mode. Setting Bit D0 low places the AD80066 into a very low power sleep mode. All register contents are retained while the AD80066 is in the power-down state. the CDSCLK2 pulse always resets the multiplexer to sample the A channel first. When Bit D4 is set high, the channel order is reversed to D, C, B, and A. The CDSCLK2 pulse always resets the multiplexer to sample the D channel first. Bits D[3:0] are used when operating in 1-channel mode. Bit D3 is set high to sample the A channel. Bit D2 is set high to sample the B channel. Bit D1 is set high to sample the C channel. Bit D0 is set high to sample the D channel. The multiplexer remains stationary in 1-channel mode.
PGA GAIN REGISTERS
There are four PGA registers for individually programming the gain for the A, B, C, and D channels. The D8, D7, and D6 bits in each register must be set low, and the D5 through D0 bits control the gain range in 64 increments. See Figure 22 for the PGA gain vs. the PGA register value. The coding for the PGA registers is straight binary, with a word of all 0s corresponding to the minimum gain setting (1x) and a word of all 1s corresponding to the maximum gain setting (5.9x).
OFFSET REGISTERS
There are four offset registers for individually programming the offset in the A, B, C, and D channels. The D8 through D0 bits control the offset range from -300 mV to +300 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. Table 11 shows the offset range as a function of the D8 through D0 bits.
MUX REGISTER
The mux register controls the sampling channel order in the AD80066. The D8, D7, D6, and D5 bits should always be set low. Bit D4 is used when operating in 4-channel mode. Setting Bit D4 low sequences the multiplexer to sample the A channel first, and then the B, C, and D channels. When in this mode, Table 8. Configuration Register Settings
D8 Set to 0 D7 Set to 0 D6 Set to 0 D5 Internal voltage reference 1 = disabled 0 = enabled 1 D4 2/1 byte output 1 = one byte 0 = two bytes1
D3 CDS operation 1 = SHA mode 0 = CDS mode1
D2 Input range 1=3V 0 = 1.5 V1
D1 Fast/slow 1 = 8 MHz 0 = 24 MHz1
D0 Power mode 1 = on (normal) 0 = off1
1
Power-on default.
Table 9. Mux Register Settings
D8 Set to 0 D7 Set to 0 D6 Set to 0 D5 Set to 0 D4 Mux order 1 = D, C, B, A 0 = A, B, C, DD1 D3 Channel A 1 = channel used 0 = not used1 D2 Channel B 1 = channel used 0 = not used1 D1 Channel C 1 = channel used 0 = not used1 D0 Channel D 1 = channel used 0 = not used1
1
Power-on default.
Table 10. PGA Gain Register Settings
D8 1 0 0 ... 0 0
1 2
D71 0 0 ... 0 0
D61 0 0 ... 0 0
(MSB) D5 0 0 ... 1 1
D4 0 0 ... 1 1
D3 0 0 ... 1 1
D2 0 0 ... 1 1
D1 0 0 ... 1 1
(LSB) D0 02 1 ... 0 1
Gain (V/V) 1.0 1.013 ... 5.56 5.9
Gain (dB) 0.0 0.12 ... 14.9 15.56
Must be set to 0. Power-on default. Rev. A | Page 15 of 20
AD80066
Table 11. Offset Register Settings
(MSB) D8 0 0 ... 0 1 1 ... 1
1
D7 0 0 ... 1 0 0 ... 1
D6 0 0 ... 1 0 0 ... 1
D5 0 0 ... 1 0 0 ... 1
D4 0 0 ... 1 0 0 ... 1
D3 0 0 ... 1 0 0 ... 1
D2 0 0 ... 1 0 0 ... 1
D1 0 0 ... 1 0 0 ... 1
(LSB) D0 01 1 ... 1 0 1 ... 1
Offset (mV) 0 +1.2 ... +300 0 -1.2 ... -300
Power-on default value.
Rev. A | Page 16 of 20
AD80066 CIRCUIT OPERATION
ANALOG INPUTS--CDS MODE
Figure 17 shows the analog input configuration for the CDS mode of operation. Figure 18 shows the internal timing for the sampling switches. The CCD reference level is sampled when CDSCLK1 transitions from high to low, opening S1. The CCD data level is sampled when CDSCLK2 transitions from high to low, opening S2. S3 is then closed, generating a differential output voltage that represents the difference between the two sampled levels. The input clamp is controlled by CDSCLK1. When CDSCLK1 is high, S4 closes and the internal bias voltage is connected to the analog input. The bias voltage charges the external 0.1 F input capacitor, level-shifting the CCD signal into the input common-mode range of the AD80066. The time constant of the input clamp is determined by the internal 5 k resistance and the external 0.1 F input capacitance.
AD80066
CCD SIGNAL CIN 0.1F VINA
S1
EXTERNAL INPUT COUPLING CAPACITORS
The recommended value for the input coupling capacitors is 0.1 F. Although it is possible to use a smaller capacitor, this larger value is preferable for several reasons: * Signal attenuation: The input coupling capacitor creates a capacitive divider using the input capacitance from an integrated CMOS circuit, which, in turn, attenuates the CCD signal level. CIN should be large relative to the 10 pF input capacitance of the IC in order to minimize this effect. Linearity: Some of the input capacitance of a CMOS IC is junction capacitance, which varies nonlinearly with applied voltage. If the input coupling capacitor is too small, the attenuation of the CCD signal varies nonlinearly with signal level. This degrades the system linearity performance. Sampling errors: The internal 2 pF sampling capacitors retain a memory of the previously sampled pixel. There is a charge redistribution error between CIN and the internal sample capacitors for larger pixel-to-pixel voltage swings. As the value of CIN is reduced, the resulting error in the sampled voltage increases. With a CIN value of 0.1 F, the charge redistribution error is less than 1 LSB for a full-scale, pixelto-pixel voltage swing.
*
*
2pF CML
5k
S2
S3 CML 2pF
S4 OFFSET 1F + 0.1F 3V
AVDD 1.7k 2.2k 6.9k
Figure 17. CDS Mode Input Configuration (All Four Channels Are Identical)
S1, S4 CLOSED CDSCLK1 S1, S4 OPEN S2 CLOSED CDSCLK2 S2 OPEN S3 CLOSED Q3 (INTERNAL) S3 OPEN S3 CLOSED
08552-018
S1, S4 CLOSED
S2 CLOSED
Figure 18. CDS Mode Internal Switch Timing
08552-017
Rev. A | Page 17 of 20
AD80066
ANALOG INPUTS--SHA MODE
Figure 19 shows the analog input configuration for the SHA mode of operation. Figure 20 shows the internal timing for the sampling switches. The input signal is sampled when CDSCLK2 transitions from high to low, opening S1. The voltage on the OFFSET pin is also sampled on the falling edge of CDSCLK2, when S2 opens. S3 is then closed, generating a differential output voltage that represents the difference between the sampled input voltage and the OFFSET voltage. The input clamp is disabled during SHA mode operation.
AD80066
VINA INPUT SIGNAL OFFSET OPTIONAL DC OFFSET (OR CONNECT TO GND) VINB S2 S3 2pF S1 2pF CML A CML
AD80066
VINA
SHA
A OFFSET
VINB
SHA
B OFFSET
VOLTAGE REFERENCE FROM CIS MODULE AVDD R1 DC OFFSET R2
VINC
SHA
C OFFSET
OFFSET 0.1F
08552-021
Figure 21. SHA Mode Used with External DC Offset
CML B CML
PROGRAMMABLE GAIN AMPLIFIERS (PGA)
The AD80066 uses one PGA for each channel. Each PGA has a gain range from 1x (0 dB) to 5.8x (15.5 dB), adjustable in 64 steps. Figure 22 shows the PGA gain as a function of the PGA register value. Although the gain curve is approximately linear-in-dB, the gain in V/V varies nonlinearly with register code, following the equation
VINC
CML C CML
VIND
CML
08552-019
Gain =
D CML
5.9 63 - G 1 + 4.9 63
Figure 19. SHA Mode Input Configuration (All Four Channels Are Identical)
S1, S2 CLOSED CDSCLK2 S1, S2 OPEN S3 CLOSED Q3 (INTERNAL) S3 OPEN S3 CLOSED
08552-020
where G is the decimal value of the gain register contents and varies from 0 to 63.
15
S1, S2 CLOSED
5.9
12
5.0
Figure 20. SHA Mode Internal Switch Timing
0
4
PGA REGISTER VALUE (Decimal)
Figure 22. PGA Gain Transfer Function
Rev. A | Page 18 of 20
08552-022
Figure 21 shows how the OFFSET pin can be used in a CIS application for coarse offset adjustment. Many CIS signals have dc offsets ranging from several hundred millivolts to more than 1 V. By connecting the appropriate dc voltage to the OFFSET pin, the large dc offset is removed from the CIS signal. Then, the signal can be scaled using the PGA to maximize the dynamic range of the ADC.
6
3.0
3
2.0
0
1.0 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63
GAIN (V/V)
GAIN (dB)
9
4.0
AD80066 APPLICATIONS INFORMATION
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 23 shows the recommended circuit configuration for 4-channel CDS mode operation. The recommended input coupling capacitor value is 0.1 F (see the Analog Inputs--CDS Mode section). A single ground plane is recommended for the AD80066. A separate power supply can be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the AD80066. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of
5V 0.1F 0.1F CLOCK INPUTS AVDD CDSCLK1 CDSCLK2 3.3V ADCCLK DRVDD 0.1F DRVSS (MSB) D7 D6 D5 D4 D3 D2 D1 (LSB) D0 DATA INPUTS
1 2 3 4 5 6 7 28 27 26 25 24
CDSCLK2 should occur coincident with or before the rising edge of ADCCLK (see Figure 3 through Figure 8 for timing). All 0.1 F decoupling capacitors should be located as close as possible to the AD80066 pins. When operating in 1-channel mode, the unused analog inputs should be grounded. Figure 24 shows the recommended circuit configuration for 4-channel SHA mode. All of the previously explained considerations also apply to this configuration, except that the analog input signals are directly connected to the AD80066 without the use of coupling capacitors. Before connecting the signals, the analog input signals must be dc-biased between 0 V and 1.5 V or 3 V (see the Analog Inputs--SHA Mode section).
0.1F A INPUT AVSS VINA OFFSET VINB CML VINC CAPT CAPB VIND AVSS AVDD SLOAD SCLK SDATA 5V SERIAL INTERFACE
08552-023
B INPUT
0.1F
0.1F
1.0F 0.1F 0.1F C INPUT
AD80066
TOP VIEW
23 22
8 (Not to Scale) 21 9 10 11 12 13 14 20 19 18 17 16 15
0.1F
10F
0.1F
0.1F D INPUT
0.1F
Figure 23. Recommended Circuit Configuration, 4-Channel CDS Mode
5V 0.1F A INPUT AVSS VINA OFFSET VINB CML VINC CAPT CAPB VIND AVSS AVDD SLOAD SCLK SDATA 5V SERIAL INTERFACE
08552-024
AVDD CLOCK INPUTS 2 3.3V CDSCLK1 CDSCLK2 ADCCLK DRVDD 0.1F DRVSS (MSB) D7 D6 D5 D4 D3 D2 D1 (LSB) D0 DATA INPUTS
B INPUT
1 2 3 4 5 6 7
28 27 26 25 24 23
0.1F C INPUT
AD80066
TOP VIEW
22
0.1F 0.1F 10F 0.1F
8 (Not to Scale) 21 9 10 11 12 13 14 20 19 18 17 16 15
D INPUT 0.1F
Figure 24. Recommended Circuit Configuration, 4-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
Rev. A | Page 19 of 20
AD80066 OUTLINE DIMENSIONS
10.50 10.20 9.90
28
15
5.60 5.30 5.00
1 14
8.20 7.80 7.40
2.00 MAX
1.85 1.75 1.65 0.38 0.22 SEATING PLANE 8 4 0
0.25 0.09
0.05 MIN COPLANARITY 0.10 0.65 BSC
0.95 0.75 0.55
060106-A
COMPLIANT TO JEDEC STANDARDS MO-150-AH
Figure 25. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD80066KRSZ AD80066KRSZRL
1
Temperature Range 0C to 70C 0C to 70C
Package Description 28-Lead SSOP 28-Lead SSOP
Package Option RS-28 RS-28
Z = RoHS Compliant Part.
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08552-0-4/10(A)
Rev. A | Page 20 of 20

▲Up To Search▲

Price & Availability of AD80066KRSZ

	To Download AD80066KRSZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .